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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75312(A), 75316(A)
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75316(A) is one of the 75X Series 4-bit single-chip microcomputer having a built-in LCD controller/ driver, and has a data processing capability comparable to that of an 8-bit microcomputer. In addition to high-speed operation with 0.95 s minimum instruction execution time for the CPU, the
PD75316(A) can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer
chip having a built-in LCD panel controller/driver, its data processing capability is the highest in its class in the world.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
PD75308 User's Manual: IEM-5016
FEATURES
* Higher reliability than PD75316 * Internal memory * Program memory (ROM) : 16256 x 8 bits (PD75316(A)) : 12160 x 8 bits (PD75312(A)) * Data memory : 512 x 4 bits * Capable of high-speed operation and variable instruction execution time to power save * 0.95 s, 1.91 s, 15.3 s (operating at 4.19 MHz) * 122 s (operating at 32.768 kHz) * 75X architecture comparable to that for an 8-bit microcomputer is employed * Built-in programmable LCD controller/driver * Clock operation at reduced power dissipation: 5 A TYP. (operating at 3 V) * Enhanced timer function (3 channels) * Interrupt functions especially enhanced for applications, such as remote control receiver * Pull-up resistors can be provided for 31 I/O lines * Built-in NEC standard serial bus interface (SBI) * Upgraded model of PD7514 (PD7500 Series) * PROM version (PD75P316, PD75P316A) available
APPLICATIONS
Suitable for controlling automotive and transportation equipment.
The PD75316(A) is treated as the representative model throughout this document, unless there are differences between PD75312(A) and PD75316(A) functions.
The information in this document is subject to change without notice.
Document No. IC-2825A (O. D. No. IC-8270A) Date Published December 1993 P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1991
PD75312(A), 75316(A)
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14x20 mm) 80-pin plastic QFP (14x20 mm) Quality Grade Special Special
PD75312GF(A)-xxx-3B9 PD75316GF(A)-xxx-3B9
Remarks: xxx is ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
DIFFERENCE BETWEEN PD75316(A) and PD75316
Product Item Quality Grade Directly Driving LED Absolute Maximum Ratings Electrical Characteristics DC Characteristics Special Not offered Standard Offered
PD75316(A)
PD75316
Differ in high-level output currrent and low-level output current Differ in low-level output voltage
2
PD75312(A), 75316(A)
FUNCTIONAL OUTLINE (1/2)
Item Number of Basic Instructions Instruction Cycle Internal Memory ROM RAM 41 * 0.95 s, 1.91 s, 15.3 s (Main system clock: operating at 4.19 MHz) * 122 s (Subsystem clock: operating at 32.768 kHz) 16256 x 8-bit (PD75316(A)), 12160 x 8-bit (PD75312(A)) 512 x 4 bits * 4-bit manipulation: 8 (B, C, D, E, H, L, X, A) * 8-bit manipulation: 4 (BC, DE, HL, XA) * Bit accumulator (CY) * 4-bit accumulator (A) * 8-bit accumulator (XA) * * * * Abundant bit manipulation instructions Efficient 4-bit data manipulation instructions 8-bit data transfer instructions GETI instruction executing 2-/3-byte instruction with a single byte 8 16 8 8 CMOS input pins CMOS input/output pins CMOS output pins N-ch open-drain input/output Also serve as segment pins Withstand voltage: 10 V Pull-up by mask option is possible. :8 Pull-up by software is possible. : 23 Function
General-Purpose Registers Accumulator
Instruction Set
I/O Line
40
LCD Controller/ Driver
* Segment number selection: 24/28/32 segments (4/8 pins can also be used as bit ports.) * Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty * Dividing resistor for LCD driving can be built-in by mask option.
Supply Voltage Range Timer
VDD = 2.7 to 6.0 V 3 chs * 8-bit timer/event counter * Clock source: 4 steps * Event count is possible * 8-bit basic interval timer * Reference time generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms (operating at 4.19 MHz) * Can be used as watchdog timer * Watch timer * Generates 0.5-second time intervals * Count clock source: Main system clock or subsystem clock (selectable) * Watch fast forward mode (generates 3.9-ms time intervals) * Buzzer output (2 kHz)
3
PD75312(A), 75316(A)
FUNCTIONAL OUTLINE (2/2)
Item 8-bit Serial Interface * Three modes: * 3-line serial I/O mode * 2-line serial I/O mode * SBI mode * LSB/MSB first selectable Bit Sequential Buffer Clock Output Function Special bit manipulation memory: 16 bits * Ideal for remote controller Timer/event counter output (PTO0): Output of square wave at specified frequency Clock output (PCL): , 524, 262, 65.5 kHz (operating at 4.19 MHz) Buzzer output (BUZ): 2 kHz (operating at 4.19 MHz or 32.768 kHz) Vector Interrupt Test Input System Clock Oscillator Circuit Standby Package * External: 3 * Internal: 3 * External: 1 * Internal: 1 * Ceramic/crystal oscillator circuit for main system clock oscillation: 4.194304 MHz * Crystal oscillator circuit for subsystem clock oscillation: 32.768 kHz STOP/HALT mode 80-pin plastic QFP (14 x 20 mm) Function
4
PD75312(A), 75316(A)
CONTENTS 1. PIN CONFIGURATION (Top View) ................................................................................................ 7
2.
BLOCK DIAGRAM ...........................................................................................................................
8
3. PIN FUNCTIONS ..............................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS ............................................................................................................................................. NON PORT PINS ................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................
9
9 11 13 15 16
4.
MEMORY CONFIGURATION ..........................................................................................................
16
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS .................................................................................................................................................... CLOCK GENERATOR CIRCUIT ............................................................................................................ CLOCK OUTPUT CIRCUIT .................................................................................................................... BASIC INTERVAL TIMER ..................................................................................................................... WATCH TIMER ...................................................................................................................................... TIMER/EVENT COUNTER ..................................................................................................................... SERIAL INTERFACE .............................................................................................................................. LCD CONTROLLER/DRIVER .................................................................................................................. BIT SEQUENTIAL BUFFER ...................................................................................................................
20
20 21 22 23 24 25 27 29 31
6.
INTERRUPT FUNCTIONS ................................................................................................................
31
7.
STANDBY FUNCTIONS ..................................................................................................................
33
8.
RESET FUNCTION ...........................................................................................................................
34
9.
INSTRUCTION SET .........................................................................................................................
36
10. SELECTION OF MASK OPTION .....................................................................................................
42
11. ELECTRICAL SPECIFICATIONS ......................................................................................................
43
12. PACKAGE DRAWINGS ...................................................................................................................
55
5
PD75312(A), 75316(A)
13. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 57
APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS .....................
58
APPENDIX B. DEVELOPMENT TOOLS ..............................................................................................
59
APPENDIX C.
RELATED DOCUMENTS ..............................................................................................
60
6
PD75312(A), 75316(A)
1. PIN CONFIGURATION (Top View)
S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P72/KR6 P71/KR5
S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S25/BP1 S26/BP2 S27/BP3 S28/BP4 S29/BP5 S30/BP6 S31/BP7 COM0 COM1 COM2 COM3
80 79 78 77 76 75 74 73 72 7170 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 X2 X1 NC XT2 XT1 VDD P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
PD75312GF(A) - xxx-3B9
P00-P03 : Port 0 P10-P13 : Port 1 P20-P23 : Port 2 P30-P33 : Port 3 P40-P43 : Port 4 P50-P53 : Port 5 P60-P63 : Port 6 P70-P73 : Port 7 BP0-BP7 : Bit Port KR0-KR7 : Key Return SCK SI SO RESET : Serial Clock : Serial Input : Serial Output : Reset Input
SB0, SB1 : Serial Bus 0,1
BIAS V LC0 V LC1 V LC2 P40 P41 P42 P43 V SS P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0
PD75316GF(A) - xxx-3B9
S0-S31 COM0-COM3 VLC0-VLC2 BIAS LCDCL SYNC TI0 PTO0 BUZ PCL INT2 X1, X2 XT1, XT2 NC
: Segment Output 0-31 : Common Output 0-3 : LCD Power Supply 0-2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0 : Programmable Timer Output 0 : Buzzer Clock : Programmable Clock : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : No Connection
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
7
8
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 PROGRAM COUNTER (14) CY ALU BANK SP (8)
PORT 0
4
P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
PORT 3
4
P30-P33
BUZ/P23
WATCH TIMER GENERAL REG. INTW f LCD PROGRAM MEMORY (ROM) 16256 x 8 BITS PD75316(A) : 12160 x 8 BITS : PD75312(A)
PORT 4
4
P40-P43
PORT 5
4
P50-P53
SI/SB1/P03 SO/SB0/P02 SCK/P01
PORT 6 DECODE AND CONTROL DATA MEMORY (RAM) 512 x 4 BITS
4
P60-P63
CLOCKED SERIAL INTERFACE INTCSI
PORT 7
4
P70-P73
24 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR7/P73 INTERRUPT CONTROL 8 CLOCK OUTPUT CONTROL LCD CONTROLLER /DRIVER STAND BY CONTROL CPU CLOCK f LCD 8
S0-S23 S24/BP0 -S31/BP7 COM0-COM3
PD75312(A), 75316(A)
4
f X /2 N CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN
3
V LC0 -V LC2 BIAS LCDCL/P30 SYNC/P31
BIT SEQ. BUFFER (16)
PCL/P22
XT1 XT2 X1
X2
V DD
V SS RESET
PD75312(A), 75316(A)
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Input/ Output Circuit TYPE * B
Pin Name Input/Output
Also Served As
Function
8-Bit I/O
When Reset
P00
Input Input/ Output Input/ Output Input/ Output
INT4
P01 P02
SCK SO/SB0
4-bit input port (PORT0) Pull-up resistors can be specified in 3-bit units for the P01 to P03 pins by software.
F -A x Input F -B
P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33
SI/SB1 INT0 With noise elimination function 4-bit input port (PORT1) Internal pull-up resistors can be specified in 4-bit units by software. x Input
M -C
Input
INT1 INT2 TI0 PTO0
B -C
Input/ Output
-- PCL BUZ LCDCL
4-bit input/output port (PORT2) Internal pull-up resistors can be specified in 4-bit units by software.
x
Input
E-B
Input/ Output
SYNC -- --
Programmable 4-bit input/output port (PORT3) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4) Internal pull-up resistors can be specified in bit units. (mask option) Withstand voltage is 10 V in the opendrain mode.
x
Input
E-B
P40-43
Input/ Output
--
q Input/ Output N-ch open-drain 4-bit input/output port (PORT5) Internal pull-up resistors can be specified in bit units. (mask option) Withstand voltage is 10 V in the opendrain mode.
High level (with internal pull-up resistor) or high impedance High level (with internal pull-up resistor) or high impedance
M
P50-53
--
M
*: Circles indicate Schmitt trigger inputs.
9
PD75312(A), 75316(A)
3.1 PORT PINS (2/2)
Input/ Output Circuit TYPE*1
Pin Name Input/Output
Also Served As KR0
Function
8-Bit I/O
When Reset
P60 P61 P62 P63 P70 P71 P72 P73 BP0 BP1 Output BP2 BP3 BP4 BP5 BP6 BP7 Output Input/ Output Input/ Output
KR1 KR2 KR3 KR4 KR5 KR6 KR7 S24 S25 S26 S27 S28 S29 S30 S31
Programmable 4-bit input/output port (PORT6) This port can be specified for input/ output in bit units. Internal pull-up resistors can be specified in 4-bit units by software.
Input q
F -A
4-bit input/output port (PORT7) Internal pull-up resistors can be specified in 4-bit units by software.
Input
F -A
1-bit output port (BIT PORT) Shared with a segment output pin.
x
*2
G-C
*1: Circles indicate Schmitt trigger inputs. 2: For BP0-7, VLC1 indicated below are selected as the input source. However, the output level is changed depending on BP0-7 and the VLC1 external circuits. Example: Since BP0-7 are connected to each other within the PD75316(A) as shown in the diagram below, the output level of BP0-7 depends on the sizes of R1, R2 and R3.
PD75316(A)
V DD
R2 BP0 V LC1 ON
R1 ON
BP1
R3
10
3
PD75312(A), 75316(A)
3.2 NON PORT PINS
Input/ Output Circuit TYPE*1 B -C E-B E-B E-B F -A F -B M -C B
Also Served Pin Name Input/Output As TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 Input INT1 INT2 Input Input/ Output Input/ Output Output Output Output -- Output Input/ Output Input/ Output P11 P12 Input Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input/ Output Input P13 P20 P22 P23 P01 P02 P03 P00 P10
Functon
When Reset
Timer/event counter external event pulse Input Timer/event counter output Clock output Fixed frequency output (for buzzer or for trimming the system clock) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vector interrupt input (both rising and falling edge detection are effective) Edge detection vector interrupt input (detection edge can be selected) Clock synchronous
Input Input Input Input Input Input Input Input
Input Asynchronous Input
B -C
Edge detection testable Asynchronous input (rising edge detection) Parallel falling edge detection testable input Parallel falling edge detection testable input Segment signal output Segment signal output Common signal output LCD drive power Internal dividing resistor (mask option) Disconnect output for external expanded driver Externally expanded driver clock output Externally expanded driver sync clock output To connect the crystal/ceramic oscillator to the main system clock generator. When inputting the external clock, input the external clock to pin X1, and the reverse phase of the external clock to pin X2. To connect the crystal oscillator to the subsystem clock generator. When the external clock is used, pin XT1 inputs the external clock. In this case, pin XT2 must be left open. Pin XT1 can be used as a 1-bit input (test) pin.
B -C
KR0-KR3 KR4-KR7 S0-S23 S24-S31 COM0COM3 VLC0-VLC2 BIAS LCDCL*4 SYNC*4
P60-P63 P70-P73 -- BP0-7 -- -- -- P30 P31
Input Input *2 *2 *2 -- *3 Input Input
F -A F -A G-A G-C G-B -- -- E-B E-B
X1, X2
Input
--
--
--
XT1
Input
--
--
--
XT2
--
--
(to be cont'd)
11
PD75312(A), 75316(A)
(cont'd)
Input/ Output Circuit TYPE*1 B -- -- --
Pin Name Input/Output Also Served As RESET NC *5 VDD VSS Input -- -- -- -- -- -- --
Function
When Reset
System reset input No connection Positive power supply GND
-- -- -- --
*1: Circles indicate Schmitt trigger inputs. 2: For these display output, VLCX indicated below are selected as the input source. S0 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output level varies depending on the particular display output and VLCX external circuit. 3: Internal dividing resistor provided Internal dividing resistor not provided pins P30 and P31. 5: When sharing the printed circuit board with the PD75P316 and 75P316A, the NC pin must be connected to VDD. : Low level : High impedance
4: These pins are provided for future system expansion. At present, these pins are used only as
12
PD75312(A), 75316(A)
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the PD75316(A).
TYPE A (for TYPE E-B)
VDD
TYPE D (for TYPE E- B, F- A)
VDD data P-ch P-ch OUT
IN N-ch output disable
N-ch
Input buffer of CMOS standard
Push-pull output that can be set in a output high-impedance state (both P-ch and N-ch are off) TYPE E-B
TYPE B
VDD P.U.R. P.U.R. enable P-ch
IN data Type D output disable IN/OUT
Type A
Schmitt trigger input with hysteresis characteristics
P.U.R. : Pull-Up Resistor
TYPE B-C
TYPE F-A
VDD P.U.R. P.U.R. enable P-ch
VDD P.U.R. P-ch P.U.R. enable
data Type D output disable
IN/OUT
IN
Type B
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
13
PD75312(A), 75316(A)
TYPE F-B
VDD P.U.R. P.U.R. enable VDD P-ch P-ch
TYPE G- C
V DD P-ch
output disable (P) data output disable
V LC0 V LC1
IN/OUT N-ch output disable (N) SEG data/Bit Port data
P-ch OUT N-ch V LC2 N-ch
P.U.R. : Pull-Up Resistor
TYPE G-A
TYPE M
VDD P.U.R. enable (Mask option) P-ch data P-ch output disable
V LC0
IN/OUT
V LC1 SEG data N-ch V LC2 N-ch
N-ch
OUT
Middle voltage input buffer (withstand voltage: +10 V) P.U.R. : Pull-Up Resistor
TYPE G-B
TYPE M-C
VDD
V LC0 P-ch V LC1 P-ch N-ch OUT COM data N-ch P-ch V LC2 N-ch data output disable P.U.R. enable
P.U.R. P-ch IN/OUT N-ch
P.U.R. : Pull-Up Resistor
14
PD75312(A), 75316(A)
3.4 RECOMMENDED PROCESSING OF UNUSED PINS
Table 3-1 Unused Pins Processing
Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30/LCDCL P31/SYNC P32 P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 S0-S23 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 BIAS XT1 XT2 Connect to VSS Connect to VSS only when all of the VLC0-VLC2 pins are unused, otherwise, open. Connect to VSS or VDD Open Open Input : Connect to VSS or VDD Output: Open Connect to VSS Connect to VSS or VDD Recommended Connections Connect to VSS
15
PD75312(A), 75316(A)
3.5 NOTES ON USING THE P00/INT4, AND RESET PINS
In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the PD75316(A) are tested, is provided to the P00/INT4 and RESET pins. If a voltage exceeding VDD is applied to either of these pins, the PD75316(A) is put into test mode. Therefore, even when the PD75316(A) is in normal operation, if noise exceeding the VDD is input into any of these pins, the PD75316(A) will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below. * Connect a diode having a low VF across P00/INT4 and RESET, and VDD.
VDD
* Connect a capacitor across P00/INT4 and RESET, and VDD.
VDD
Low VF diode P00/INT4, RESET
VDD
VDD
P00/INT4, RESET
4. MEMORY CONFIGURATION
* Program memory (ROM) ...16256 x 8 bits (0000H-3F7FH): PD75316(A) ...12160 x 8 bits (0000H-2F7FH): PD75312(A) * 0000H, 0001H : Vector table to which address from which program is started is written after reset * 0002H-000BH: Vector table to which address from which program is started is written after interrupt * 0020H-007FH : Table area referenced by GETI instruction * Data memory * Data area .... 512 x 4 bits (000H-1FFH) * Peripheral hardware area .... 128 x 4 bits (F80H-FFFH)
16
PD75312(A), 75316(A)
(a) PD75316(A)
Address 7 0000H MBE 6 0 5 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE 0 INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE 0 INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) BRCB ! caddr instruction branch address BR $addr instruction relational branch address (-15 to -1, +2 to +16) CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0
BR ! addr instruction branch address
0020H GETI instruction reference table 007FH 0080H
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH 1000H BRCB ! caddr instruction branch address 1FFFH 2000H BRCB ! caddr instruction branch address 2FFFH 3000H BRCB ! caddr instruction branch address 3F7FH
Fig. 4-1 Program Memory Map (1/2)
17
PD75312(A), 75316(A)
(b) PD75312(A)
Address 7 0000H MBE 6 0 5 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE 0 INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE 0 INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE 0 INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) 0008H MBE 0 INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE 0 INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) BRCB ! caddr instruction branch address BR $addr instruction relational branch address (-15 to -1, +2 to +16) CALLF ! faddr instruction entry address CALL ! addr instruction subroutine entry address 0
BR ! addr instruction branch address
0020H GETI instruction reference table 007FH 0080H
07FFH 0800H
Branch destination address and subroutine entry address for GETI instruction
0FFFH 1000H
BRCB ! caddr instruction branch address 1FFFH 2000H
BRCB ! caddr instruction branch address 2F7FH
Fig. 4-1 Program Memory Map (2/2)
18
PD75312(A), 75316(A)
Data memory General-purpose register area Stack area 000H 007H 008H 256x 4 (248 x 4) Data area Static RAM (512 x 4) 0FFH 100H 256x 4 (224 x 4) 1DFH 1E0H Display data memory area 1FFH Unmapped F80H Peripheral hardware area 128x 4 FFFH (32 x 4) (8 x 4)
Memory bank
0
1
15
Fig. 4-2 Data Memory Map
19
PD75312(A), 75316(A)
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS : : : 8 8 8
I/O ports are classified into the following 4 kinds: * CMOS input (PORT0, 1) * CMOS input/output (PORT2, 3, 6, 7) * N-ch open-drain (PORT4, 5) * CMOS output (BP0-BP7) Total : 16
: 40
Port Name PORT0
Function
Operation and Feature
Remarks Multiplexed with INT4, SCK, SO/SB0, and SI/SB1 Multiplexed with INT0INT2 and TI0 Multiplexed with PTO0, PCL, and BUZ Multiplexed with KR4-KR7 Multiplexed with LCDCL and SYNC Multiplexed with KR0-KR3
4-bit input PORT1 PORT2 PORT7 4-bit Input/Output PORT3 PORT6 PORT4 PORT5 4-bit Input/Output (N-ch open-drain, 10 V) 1-bit output
Can be always read or tested regardless of operation mode of multiplexed pin.
Can be set in input or output mode in 4-bit units. Ports 6 and 7 are used in pairs to input/output data in 8-bit units.
Can be set in input or output mode in 1-bit units.
Can be set in input or output mode in 4-bit units. Ports 4 and 5 are used in pairs to input/output data in 8-bit units. Output data in 1-bit units. Can be used as LCD drive segment output pins S24-S31 through software.
Can be connected to a pull-up resistor in 1-bit units by using mask option. Low drive capability For driving CMOS load
BP0-BP7
20
PD75312(A), 75316(A)
5.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and system clock control register (SCC). This circuit can generate two types of clocks: main system clock and subsystem clock. In addition, it can also change the instruction execution time. * 0.95 s/1.91 s/15.3 s (main system clock: 4.19 MHz) * 122 s (subsystem clock: 32.768 kHz)
* Basic interval timer (BT) * Timer/event counter * Serial interface * Watch timer * LCD controller/driver * INT0 noise rejecter circuit * Clock output circuit
V DD
XT1 XT2 X1 X2 Main system f X clock oscillator Subsystem clock oscillator f XT LCD controller /driver Watch timer
V DD
1/8 to 1/4096 Frequency divider 1/2 1/16
SCC3 Internal bus SCC0 PCC PCC0 PCC1 4 PCC2 HALT* STOP* PCC3
Oscillator disable signal
Selector
WM.3 SCC
Selector
Frequency divider 1/4 * CPU * INT0 noise rejecter circuit * Clock output circuit
HALT F/F S R Q
PCC2, PCC3 clear signal
STOP F/F Q S R
Wait release signal from BT RESET signal Standby release signal from interrupt control circuit
Remarks 1: fX = Main system clock frequency 2: fXT = Subsystem clock frequency 3: PCC: Processor clock control register 4: SCC: System clock control register 5: *: instruction execution. 6: One clock cysle (tCY) of is one machine cycle of an instruction. For tCY, refer to AC characteristics in 11. ELECTRICAL SPECIFICATIONS. 5
Fig. 5-1 Clock Generator Block Diagram
21
PD75312(A), 75316(A)
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote control output, peripheral LSIs, etc. * Clock output (PCL) : , 524, 262, 65.5 kHz (operating at 4.19 MHz) * Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz or 32.768 kHz) Fig. 5-2 shows the clock output circuit configuration.
From the clock generator fX/23 Selector fX/24 fX/26 PCL/P22 Output buffer
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM
P22 output latch
Bit 2 of PMGB
Port 2 input/ output mode specification bit
4 Internal bus
Fig. 5-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output enable/ disable is taken.
22
PD75312(A), 75316(A)
5.4 BASIC INTERVAL TIMER
The basic interval timer has these functions: * Interval timer operation which generates a reference time interrupt * Watchdog timer application which detects a program runaway * Selects the wait time for releasing the standby mode and counts the wait time * Reads out the count value
From the clock generator Clear fX/25 Clear
fX/27 MPX fX/29 BT Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
fX/212
Vector interrupt request IRQBT signal
3
Wait release signal for standby release BTM0 BTM
BTM3
BTM2
BTM1
SET1*
4 Internal bus
8
Remarks : *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
23
PD75312(A), 75316(A)
5.5 WATCH TIMER
The PD75316(A) has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4. * Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by IRQW. * 0.5 second interval can be generated either from the main system clock or subsystem clock. * Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient for program debugging, test, etc. * Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock frequency trimming. * The frequency divider circuit can be cleared so that zero second watch start is possible.
fW (512 Hz: 1.95 ms) 26 fW (256 Hz: 3.91 ms) 27 fX From the 128 (32.768 kHz) clock generator f XT (32.768 kHz) fW 2 14 (2 Hz 0.5 sec) Selector
f LCD
Selector
fW (32.768 kHz)
INTW (IRQW set signal)
Frequency divider
f W (2.048 16 kHz)
Clear Output buffer P23/BUZ
WM WM7 0 0 0 WM3 WM2 WM1 WM0 Bit test instruction Internal bus
PORT2.3
P23 output latch
Bit 2 of PMGB
Port 2 input/output mode
8
( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
Fig. 5-4 Watch Timer Block Diagram
24
PD75312(A), 75316(A)
5.6 TIMER/EVENT COUNTER The timer/even counter has these functions:
The PD75316(A) has a built-in 1-ch timer/event counter. * Programmable interval timer operation
* Outputs square-wave signal of an arbitrary frequency to the PTO0 pin. * Event counter operation * Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation). * Supplies serial shift clock to the serial interface circuit. * Count condition read out function
25
26
Internal bus 8 -- SET1*1 -- TM0 -- 8 8 TMOD0 TOE0 TO enable flag Coincidence PORT2.0 P20 output latch Bit 2 of PGMB
Port 2 input/ output mode
TM06 TM05 TM04 TM03 TM02
Modulo register (8)
PORT1.3
8 Comparator (8)
To serial interface
TOUT F/F Reset Output buffer
P20/PTO0
Input buffer P13/TI0 From the clock generator*2 MPX
8 T0 Count register (8) CP Clear Timer operation start signal
(
INTT0 IRQT0 set signal
)
PD75312(A), 75316(A)
RESET IRQT0 clear signal
*1:
SET1: Instruction execution
2: For details, refer to Fig. 5-1.
Fig. 5-5 Timer/Event Counter Block Diagram
PD75312(A), 75316(A)
5.7 SERIAL INTERFACE
The PD75316(A) is equipped with an 8-bit clocked serial interface that operates in the following three modes: * Three-line serial I/O mode * Two-line serial I/O mode * SBI mode (serial bus interface mode)
27
Selector
P02/SO/SB0
Selector
Busy/ acknowledge output circuit
Bus release/ command/ acknowledge detector circuit P01/SCK
RELD CMDD ACKD
ACKT ACKE BSYE
28
Internal bus
8/4
Bit test 8 8
8
Slave address register (SVA)
Bit manipulation (8) RELT CMDT
SET CLR
Bit test SBIC
CSIM
Coincidence signal Address comparator (8) P03/SI/SB1 Shift register (SIO) (8)
SO latch
D
Q
Serial clock counter P01 output latch
INTCSI control circuit
(
Serial clock selector
INTCSI IRQCSI set signal
)
PD75312(A), 75316(A)
Serial clock control circuit
fX/23 fX/24 fX/26 TOUT F/F (from timer/ event counter) External SCK
Fig. 5-6 Serial Interface Block Diagram
PD75312(A), 75316(A)
5.8 LCD CONTROLLER/DRIVER
The PD75316(A) is provided with a display controller that generates segment and common signals and a segment driver and a common driver that can directly drive an LCD panel. Figure 5-7 shows the LCD controller/driver configuration. These LCD controller and drivers have the following functions: * Generate segment and common signals by automatically reading the display data memory by means of DMA * Five display modes selectable
Static 1/2 duty (1/2 bias) 1/3 duty (1/2 bias)
4
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
* Four types of frame frequencies selectable in each display mode * Up to 32 segment signals (S0-S31) and four common signals (COM0-COM3) can be output. * Four segment signal output pins (S24-S27, S28-S31) can be used as an output port (BP0-BP3, BP4-BP7). * Dividing resistor for LCD driving power source can be provided (by mask option). * All bias modes and LCD drive voltages can be used. * Current flowing to dividing resistor can be cut when display is off. * Display data memory not used for display can be used as ordinary data memory. * Can also operate on subsystem clock.
29
30
Internal bus 4 Display 1FFH 1FEH data memory 3 2 1 0 3 2 1 0 1F9H 1F8H 1ECH Display mode register 32103210 3210 8 4 Display control register 4 Port 3 output latch 10 8 Port mode register group A 10 32103210 32103210 3210 Timing controller f LCD Multiplexer Selector
PD75312(A), 75316(A)
Segment driver
Common driver
LCD driving voltage control
S31/BP7
S30/BP6
S24/BP0
S23
S0
COM3 COM2 COM1 COM0 V LC2
V LC1
V LC0
P31/ SYNC
P30/ LCDCL
Fig. 5-7 LCD Controller/Driver Block Diagram
PD75312(A), 75316(A)
5.9 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units.
Address bit 3 Symbol
FC3H 2 BSB3 1 0 3
FC2H 2 BSB2 1 0 3
FC1H 2 BSB1 1 0 3
FC0H 2 BSB0 1 0
L register
L=F
L=C L=B INCS L
L=8 L=7 DECS L
L=4 L=3
L=0
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-8 Bit Sequential Buffer Format
6.
INTERRUPT FUNCTIONS
The PD75316(A) has 6 different interrupt sources and multiple interrupt by software control is also
possible. The PD75316(A) is also provided with two types of test sources, of which INT2 has two types of edge detection testable inputs. The interrupt control circuit of the PD75316(A) has these functions: * Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME). * The interrupt start address can be arbitrarily set. * Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software). * Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
31
Selector
32
Internal bus 2 IM2 1 IM1 3 IM0 Interrupt enable flag (IE xxx ) IME IST0 INT BT INT4 /P00 INT0 /P10 INT1 /P11 Both edge detection circuit Edge Noise detection elimination circuit circuit Edge detection circuit INTCSI INTT0 IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQW IRQ2 Priority control circuit Vector table address generator VRQn Decoder INTW INT2 /P12 Rising edge detection circuit Falling edge detection circuit
PD75312(A), 75316(A)
KR0/P60 KR7/P73
Standby release signal
IM2
Fig. 6-1 Interrupt Control Block Diagram
PD75312(A), 75316(A)
7. STANDBY FUNCTIONS
The PD75316(A) has two different standby modes (STOP mode and HALT mode) to reduce the power consumption while waiting for program execution.
Table 7-1 Each Status in Standby Mode
STOP Mode Setting Instruction System Clock for Setting Operation Status Clock Generator Basic Interval Timer Serial Interface STOP instrtuction Can be set only when operating on the main system clock Only the main system clock stops its operation. No operation Can operate only when the external SCK input is selected for the serial clock Can operate only when the TI0 pin input is selected for the count clock Can operate when fXT is selected for the count clock Can operate only when fXT is selected for LCDCL INT1, INT2, and INT4 can operate. Only INT0 cannot operate. No operation An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input
HALT Mode HALT instruction Can be set either with the main system clock or the subsystem clock Only the CPU clock stops its operation. (oscillation continues) Operation (Sets IRQBT at reference time interval) * Can operate *
Timer/Event Counter Watch Timer LCD Controller
Can operate *
Can operate Can operate
External Interrupt CPU Release Signal
An interrupt request signal from a hardware whose operation is enabled by the interrupt enable flag or the RESET signal input
*: Operation is possible only when the main system clock is operating.
33
PD75312(A), 75316(A)
8. RESET FUNCTION
When the RESET signal is input, the PD75316(A) is reset and each hardware is initialized as indicated in Table 8-1. Fig. 8-1 shows the reset operation timing.
Wait (31.3ms/4.19MHz) RESET input
Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware Program Counter (PC) RESET Input in Standby Mode The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. Retained 0 0 The contents of bit 7 of address 0000H of the program memory are set to MBE. Undefined Retained * Retained 0 Undefined 0 0 FFH 0 0, 0 0 RESET Input during Operation The contents of the lower 6 bits of address 0000H of the program memory are set to PC13-8, and the contents of address 0001H are set to PC7-0. Undefined 0 0 The contents of bit 7 of address 0000H of the program memory are set to MBE. Undefined Undefined Undefined 0 Undefined 0 0 FFH 0 0, 0 0
PSW
Carry Flag (CY) Skip Flag (SK0-2) Interrupt Status Flag (IST0) Bank Enable Flag (MBE)
Stack Pointer (SP) Data Memory (RAM) General-Purpose Register (X, A, H, L, D, E, B, C) Bank Selection Register (MBS) Basic Interval Counter (BT) Timer Mode Register (BTM) Timer/Event Counter Counter (T0) Module Register (TMOD0) Mode Register (TM0) TOE0, TOUT F/F Watch Timer Mode Register (WM)
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
34
PD75312(A), 75316(A)
Table 8-1 Status of Each Hardware after Reset (2/2)
Hardware Serial Interface Shift Register (SIO) Operation Mode Register (CSIM) SBI Control Register (SBIC) Slave Address Register (SVA) Clock Generator, Clock Output Circuit Processor Clock Control Register (PCC) System Clock Control Register (SCC) Clock Output Mode Register (CLOM) LCD Controller Display Mode Register (LCMD) Display Control Register (LCDC) Interrupt Function Interrupt Request Flag (IRQxxx) Interrupt Enable Flag (IExxx) Interrupt Master Enable Flag (IME) INT0, INT1, INT2 Mode Registers (IM0, 1, 2) Digital Port Output Buffer Output Latch Input/Output Mode Register (PMGA, B) Pull-Up Resistor Specification Register (POGA) Bit Sequential Buffer (BSB0-3) RESET Input in Standby Mode Retained 0 0 Retained 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0 RESET Input during Operation Undefined 0 0 Undefined 0 0 0 0 0 Reset (0) 0 0 0, 0, 0 Off Clear (0) 0 0
Retained
Specified
35
PD75312(A), 75316(A)
9. INSTRUCTION SET
(1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and - are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to PD75308 User's Manual (IEM-5016)). However, fmem and pmem restricts the label that can be described.
Representation reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem * bit fmem pmem addr caddr faddr taddr PORTn IExxx MBn
Description X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE HL, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label FB0H to FBFH,FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
PD75312(A) 0000H-2F7FH immediate data or label PD75316(A) 0000H-3F7FH immediate data or label
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (where bit0 = 0) or label PORT0 to PORT7 IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW MB0, MB1, MB15
*: Only even addresses can be described as mem for 8-bit data processing.
36
PD75312(A), 75316(A)
(2) Legend of operation field A B C D E H L X XA BC DE HL PC SP CY PSW MBE IME IExxx MBS PCC . (xx) xxH : A register; 4-bit accumulator : B register; 4-bit accumulator : C register; 4-bit accumulator : D register; 4-bit accumulator : E register; 4-bit accumulator : H register; 4-bit accumulator : L register; 4-bit accumulator : X register; 4-bit accumulator : Register pair (XA); 8-bit accumulator : Register pair (BC); 8-bit accumulator : Register pair (DE); 8-bit accumulator : Register pair (HL); 8-bit accumulator : Program counter : Stack pointer : Carry flag; or bit accumulator : Program status word : Memory bank enable flag : Interrupt mask enable flag : Interrupt enable flag : Memory bank selector register : Processor clock control register : Delimiter of address and bit : Contents addressed by xx : Hexadecimal data
PORTn : Port n (n = 0 to 7)
37
PD75312(A), 75316(A)
(3) Symbols in addressing area field
*1 *2 *3 MB = MBE . MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH Data memory addressing
*4 *5 *6 *7 *8
PD75312(A) PD75316(A)
addr = 0000H-2F7FH addr = 0000H-3F7FH
addr = (Current PC) - 15 to (Current PC) - 1 (Current PC) + 2 to (Current PC) + 16
PD75312(A)
caddr = 0000H-0FFFH (PC13 = 0, PC12 = 0) or 1000H-1FFFH (PC13 = 0, PC12 = 1) or 2000H-2F7FH (PC13 = 1, PC12 = 0) caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3F7FH (PC13 (PC13 (PC13 (PC13 = = = = 0, 0, 1, 1, PC12 PC12 PC12 PC12 = = = = 0) or 1) or 0) or 1)
Program memory addressing
PD75316(A)
*9 *10
faddr = 0000H-07FFH taddr = 0020H-007FH
Remarks 1: 2: 3: 4:
MB indicates memory bank that can be accessed. In *2, MB = 0 regardless of MBE and MBS. In *4 and *5, MB = 15 regardless of MBE and MBS. *6 to *10 indicate areas that can be addressed.
(4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: * When no instruction is skipped .................................................................................. S = 0 * When 1-byte or 2-byte instruction is skipped ........................................................... S = 1 * When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ............................ S = 2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock , (=tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC).
38
PD75312(A), 75316(A)
Machine Bytes Cycles 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 1 2 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1+S 1+S 1 1+S 1 2 1 2 1 2 1 1 2 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp reg1 A rp1 XA A (HL) A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp XA (PC13-8+DE)ROM XA (PC13-8+XA)ROM A A+n4 A A+(HL) A, CY A+(HL)+CY A A-(HL) A, CY A-(HL)-CY A A n4 A A (HL) A A n4 A A (HL) A A n4 A A (HL) CY A0, A3 CY, An-1 An AA *1 *1 *1 *1 *1 *1 *1 borrow carry carry *1 *2 *1 *3 *3 *1 *2 *1 *1 *1 *3 *3 *3 *3 String effect A String effect B Addressing Area
Instructions
Mnemonics
Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp reg1, A rp1, XA
Operation
Skip Conditions String effect A
Transfer MOV
XCH
A, @HL A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp
Table Re- MOVT ference Arithmetic Operation ADDC SUBS SUBC AND OR XOR Accumu- RORC lator Manipu- NOT lation ADDS
XA, @PCDE XA, @PCXA A, #n4 A, @HL A, @HL A, @HL A, @HL A, #n4 A, @HL A, #n4 A, @HL A, #n4 A, @HL A A
39
PD75312(A), 75316(A)
Machine Bytes Cycles 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1+S 2+S 2+S 1+S 2+S 2+S 1+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Addressing Area *1 *3
Instructions Increment/ Decrement
Mnemonics INCS
Operand reg @HL mem
Operation reg reg+1 (HL) (HL)+1 (mem) (mem)+1 reg reg-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if A = reg CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1
(fmem.bit) 1
Skip Conditions reg = 0 (HL) = 0 (mem) = 0 reg = FH reg = n4 *1 (HL) = n4
DECS
reg reg, #n4 @HL, #n4 A, @HL A, reg
Compare SKE
*1
A = (HL) A = reg
Carry flag lation Bit Manipulation
SET1 CLR1 NOT1
CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit
Manipu- SKT Memory/ SET1
CY = 1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1
(pmem7-2 + L3-2.bit(L1-0)) 1 (H + mem3-0.bit) 1
(mem.bit) 0 (fmem.bit) 0
CLR1
mem.bit fmem.bit pmem.@L @H+mem.bit
(pmem7-2 + L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1
SKT
mem.bit fmem.bit pmem.@L @H+mem.bit
Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0
Skip if (fmem.bit) = 1 and clear
SKF
mem.bit fmem.bit pmem.@L @H+mem.bit
SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit
Skip if (pmem7-2+L3-2.bit (L1-0)) = 1 and clear
Skip if (H+mem3-0.bit) = 1 and clear
CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit (L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit)
CY CY (pmem7-2+L3-2.bit (L1-0))
CY CY (H+mem3-0.bit)
40
PD75312(A), 75316(A)
Machine Bytes Cycles -- -- Addressing Area *6
Instructions Branch
Mnemonics BR
Operand addr
Operation PC13-0 addr (The most suitable instruction is selectable from among BR !addr, BRCB !caddr, and BR $addr depending on the assembler.) PC13-0 addr PC13-0 addr PC13-0 PC13,12 + caddr11-0 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, PC13, PC12 PC13-0 addr, SP SP-4 (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, PC13, PC12 PC13-0 00, faddr, SP SP-4 MBE, PC13, PC12 (SP+1)3, 1, 0 PC11-0 (SP)(SP+3)(SP+2) SP SP+4 MBE, PC13, PC12 (SP+1)3, 1, 0 PC11-0 (SP)(SP+3)(SP+2) SP SP+4, then skip unconditionally PC13, PC12 (SP+1)1, 0 PC11-0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 (SP-1)(SP-2) rp, SP SP-2 (SP-1) MBS, (SP-2) 0, SP SP-2 rp (SP+1)(SP), SP SP+2 MBS (SP+1), SP SP+2 IME 1 IExxx 1 IME 0 IExxx 0 A PORTn XA PORTn+1,PORTn PORTn A PORTn+1,PORTn XA
(n = 0-7) (n = 4, 6) (n = 2-7) (n = 4, 6)
Skip Conditions
!addr $addr BRCB Subrou- CALL tine/ Stack Control CALLF !faddr !caddr !addr
3 1 2 3
3 2 2 3
*6 *7 *8 *6
2
2
*9
RET
1
3
RETS
1
3+S
Undefined
RETI
1
3
PUSH POP Interrupt Control I/O DI EI
rp BS rp BS IExxx IExxx
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 3
IN OUT
A,PORTn XA,PORTn PORTn,A PORTn,XA
CPU Control Special
HALT STOP NOP SEL GETI MBn taddr
Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation MBS n (n = 0, 1, 15) . Where TBR instruction, PC13-0 (taddr)5-0+(taddr+1) ......................................................... . Where TCALL instruction, (SP-4)(SP-1)(SP-2) PC11-0 (SP-3) MBE, 0, PC13, PC12 PC13-0 (taddr)5-0+(taddr+1) SP SP-4 ......................................................... . Except for TBR and TCALL instructions, Instruction execution of (taddr)(taddr+1) *10 .............................
2 1
............................. Depends on referenced instruction
Note: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. Remarks: The TBR and TCALL instructions are the assembler pseudo-instructions for the table definition of GETI instruction. 41
PD75312(A), 75316(A)
10. SELECTION OF MASK OPTION
The following mask operations are available and can be specified for each pin.
Pin P40-P43, P50-P53 VLC0-VLC2, BIAS Mask Option * With pull-up resistor (Specification in bit units) * Without pull-up resistor (Specification in bit units) * With dividing resistor for LCD drive power source (Specification in 4-bit units) * Without dividing resistor for LCD drive power source (Specification in 4-bit units)
42
PD75312(A), 75316(A)
11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25C)
Parameter Supply Voltage Input Voltage Symbol VDD VI1 VI2 Other than ports 4, 5 Ports 4, 5 w/pull-up resistor Open drain Output Voltage High-Level Output Current All pins Low-Level Output Current Other than ports 0, 2, 3, 5 Total of ports 4, 6, 7 Operating Temperature Storage Temperature Topt Tstg IOL* 1 pin VO IOH 1 pin Peak rms Peak rms Peak rms Peak rms Peak rms Conditions Ratings -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to +11 -0.3 to VDD+0.3 -10 -5 -30 -5 10 5 100 60 100 50 -40 to +85 -65 to +150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C C
*: rms = Peak value x Duty
CAPACITANCE (Ta = 25C, VDD = 0 V)
Parameter Input Capacitance Output Capacitance Input/Output Capacitance Symbol CIN COUT CIO f = 1 MHz Pins other than thosemeasured are at 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF
43
PD75312(A), 75316(A)
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Ceramic *3
Item Oscillation frequency(fX)*1
Conditions
MIN. 1.0
TYP.
MAX. 5.0 *3
Unit MHz
X1 C1
X2 C2 VDD
Oscillation stabiliza- After VDD came to tion time*2 MIN. of oscillation voltage range
4
ms
Crystal *3
X1 C1 VDD X2 C2
Oscillation frequency (fX)*1 Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*2
1.0
4.19
5.0
*3
MHz ms ms
10 30
External Clock
X1 X2
X1 input frequency (fX)*1 X1 input high-, low-level widths (tXH, tXL)
1.0
5.0 *
3
MHz
PD74HCU04
100
500
ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range or the STOP mode has been released. 5 3: When the oscillation frequency is 4.19 MHz < fx 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 s, falling short of the rated minimum value of 0.95 s. SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Recommended Constants
Oscillator Crystal
Item Oscillation frequency (fXT)
Conditions
MIN. 32
TYP. 32.768 1.0
MAX. 35 2 10
Unit kHz s s
XT1
XT2 R
Oscillation stabiliza- VDD = 4.5 to 6.0 V tion time*
C3 VDD
C4
External Clock
XT1 Open XT2
XT1 input frequency (fXT)* XT1 input high-, low-level widths (tXTH, tXTL)
32
100
kHz
5
15
s
*:
Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage range.
44
PD75312(A), 75316(A)
Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VDD. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more easily than the main system clock oscillation circuit. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit.
45
PD75312(A), 75316(A)
DC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level Input Voltage VIL1 VIL2 VIL3 High-Level Output Voltage VOH1 Ports 2, 3 Ports 0, 1, 6, 7, RESET Ports 4, 5 X1, X2, XT1 Ports 2, 3, 4, 5 Ports 0, 1, 6, 7, RESET X1, X2, XT1 Ports 0, 2, 3, 6, 7 and BIAS BP0-7 (with two IOH outputs) Ports 0, 2, 3, 4, 5, 6, 7, and 8 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A VOH2 VDD = 4.5 to 6.0 V IOH = -100 A IOH = -30 A Ports 3, 4, and 5 VDD = 4.5 to 6.0 V IOL = -15 mA VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A SB0, 1 VOL2 BP0-7 (with two IOL outputs) VIN = VDD VIN = 10 V VIN = 0 V VOUT = VDD VOUT = 10 V VOUT = 0 V Ports 0, 1, 2, 3, 6, 7 VDD = 5.0 V10% (except P00) VIN = 0V VDD = 3.0 V10% Ports 4, 5 VOUT = VDD-2.0 V VDD = 5.0 V10% VDD = 3.0 V10% 15 30 15 10 2.5 60 IO = 5 A IO = 1 A VLCD0 = VLCD VLCD1 = VLCDx2/3 VLCD2 = VLCDx1/3 2.7 V VLCD VDD 0 0 100 40 40 Open-drain Pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Other than below X1, X2, XT1 Ports 4, 5 (open-drain) Other than below X1, X2, XT1 Other than below Ports 4, 5 (open-drain) w/pull-up resistor Open-drain Conditions MIN. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VDD-0.5 0 0 0 VDD-1.0 VDD-0.5 VDD-2.0 VDD-1.0 0.2 1.0 TYP. MAX. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V V V
Low-Level Output Voltage
VOL1
0.4 0.5 0.2VDD 1.0 1.0 3 20 20 -3 -20 3 20 -3 80 300 70 60 VDD 150 0.2 0.2
V V V V V
High-Level Input Leakage Current
ILIH1 ILIH2 ILIH3
A A A A A A A A
k k k k V k V V
Low-Level Input Leakage Current High-Level Output Leakage Current Low-Level Output Leakage Current
ILIL1 ILIL2 ILOH1 ILOH2 ILOL
Internal Pull-Up Resistor RL1 RL2 LCD Drive Voltage LCD Step-down Resistor LCD Output Voltage Deviation (Common) *1 LCD Output Voltage Deviation (Segment) VLCD RLCD VODC VODS
(to be cont'd)
46
PD75312(A), 75316(A)
(cont'd)
Parameter Symbol Conditions 4.19 MHz*3 crystal oscillator C1 = C2 = 22pF VDD = 5 V10%* 4 VDD = 3 V10%* 5 VDD = 5 V10% VDD = 3 V10% IDD3 IDD4 IDD5 32 crystal oscillato XT1 = 0 V STOP mode kHz*6 VDD = 3 V10% HALT mode
VDD = 3 V10%
MIN.
TYP. 2.5 0.35 500 150 30 5 0.5 0.1 0.1
MAX. 8 1.2 1500 450 90 15 20 10 5
Unit mA mA
Supply Current * 2 IDD1 IDD2
HALT mode
A A A A A A A
VDD = 3 V10%
VDD = 5 V10% Ta = 25C
*1: "Voltage deviation" means the difference between the ideal segment or common output value (VLCDn: n = 0, 1, 2) and output voltage. 2: Currents for the built-in pull-up resistor and the LCD step-down resistor are not included. 3: Including when the subsystem clock is operated. 4: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011. 5: When operated in the low-speed mode with the PCC set to 0000. 6: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to stop the main system clock operation.
47
PD75312(A), 75316(A)
AC CHARACTERISTICS (Ta = -40 to +85C, VDD = 2.7 to 6.0 V)
Parameter CPU Clock Cycle Time (Minimum Instruction Execution Time = 1 Machine Cycle)*1 TI0 Input Frequency TI0 Input High-, LowLevel Widths Interrupt Input High-, Low-Level Widths Symbol tCY Conditions w/main system clock w/sub-system clock fTI tTIH, tTIL tINTH, tINTL VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V INT0 INT1, 2, 4 KR0-7 RESET Low-Level Width tRSL VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 0.48 1.8 *2 10 10 10 122 TYP. MAX. 64 64 125 1 275 Unit
s s s
MHz kHz
s s s s s s
*1: The CPU clock ( ) cycle time is determined by the oscillation frequency of the connected oscillator, system clock control register (SCC), and processor clock control register (PCC). The figure on the right is cycle time tCY vs. supply voltage VDD characteristics at the main system clock. 2: 2tCY or 128/fX depending on the setting
Cycle time tCY [s]
6 5 4 3 Operation guaranteed range 70 64 30 tCY vs VDD (with main system clock)
of the interrupt mode register (IM0).
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
48
PD75312(A), 75316(A)
SERIAL TRANSFER OPERATION Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY1 tKL1 tKH1 Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY1/2-50 tKCY1/2-150 150 400 RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI Set-Up Time (vs. SCK ) tSIK1
SI Hold Time (vs. SCK ) tKSI1 SCK SO Output Delay Time tKSO1
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter SCK Cycle Time SCK High-, Low-Level Widths Symbol tKCY2 tKL2 tKH2 tKSI2 tKSO2 RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 400 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SI Set-Up Time (vs. SCK ) tSIK2
SI Hold Time (vs. SCK ) SCK SO Output Delay Time
*: RL and CL are load resistance and load capacitance of the SO output line.
49
PD75312(A), 75316(A)
SBI MODE (SCK: internal clock output (master))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY3 tKL3 tKH3 tSIK3 tKSI3 tKSO3 tKSB tSBK tSBL tSBH RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 1600 3800 tKCY3/2-50 tKCY3/2-150 150 tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
SBI MODE (SCK: external clock input (slave))
Parameter SCK Cycle Time SCK High-, Low-Level Widths SB0, 1 Set-Up Time (vs. SCK ) SB0, 1 Hold Time (vs. SCK ) SCK SB0, 1 Output Delay Time SCK SB0, 1 SB0,1 SCK SB0, 1 Low-Level Width SB0, 1 High-Level Width Symbol tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 tKSB tSBK tSBL tSBH RL = 1 k, CL = 100 pF* VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 800 3200 400 1600 100 tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
*: RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
50
PD75312(A), 75316(A)
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
0.8 VDD Test points 0.2 VDD
0.8 VDD 0.2 VDD
CLOCK TIMING
1/fX tXL tXH
X1 input
VDD -0.5V 0.4 V
1/fXT tXTL tXTH
XT1 input
VDD -0.5V 0.4 V
TI0 TIMING
1/fTI tTIL tTIH
TI0
51
PD75312(A), 75316(A)
SERIAL TRANSFER TIMING THREE-LINE SERIAL I/O MODE:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
TWO-LINE SERIAL I/O MODE:
tKCY2 tKL2 tKH2
SCK
tKSO2
tSIK2
tKSI2
SB0,1
52
PD75312(A), 75316(A)
SERIAL TRANSFER TIMING BUS RELEASE SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1 tKSO3,4
COMMAND SIGNAL TRANSFER:
tKCY3,4 tKL3,4 SCK tSIK3,4 tKH3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
INTERRUPT INPUT TIMING:
tINTL
tINTH
INT0, 1, 2, 4 KR0-7
RESET INPUT TIMING:
tRSL
RESET
53
PD75312(A), 75316(A)
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = -40 to +85C)
Parameter Data Retention Supply Voltage Data Retention Supply Current*1 Release Signal Set Time Oscillation Stabilization Wait Time*2 Symbol VDDDR IDDDR tSREL tWAIT Released by RESET Released by interrupt VDDDR = 2.0 V 0 217 /fX *3 Conditions MIN. 2.0 0.1 TYP. MAX. 6.0 10 Unit V
A s
ms ms
*1: Does not include current flowing through internal pull-up resistor 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT time ( ): fX = 4.19 MHz 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
DATA RETENTION TIMING
(releasing STOP mode by RESET)
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution RESET tSREL
tWAIT
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
HALT mode STOP mode Data retention mode Operation mode
VDD VDDDR STOP instruction execution Standby release signal (interrupt request) tSREL
tWAIT
54
PD75312(A), 75316(A)
12. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
55
PD75312(A), 75316(A)
13. RECOMMENDED SOLDERING CONDITIONS
It is recommended that PD75316(A) be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). The soldering methods and conditions are not listed here, consult NEC.
Table 13-1 Soldering Conditions
PD75312GF(A) - xxx - 3B9: 80-pin plastic QFP (14x20 mm) PD75316GF(A) - xxx - 3B9: 80-pin plastic QFP (14x20 mm)
Soldering Method Infrared Reflow Soldering Conditions Package peak temperature: 230C, time: 30 seconds max. (210C min.), number of times: 1 Package peak temperature: 215C, time: 40 seconds max. (200C min.), number of times: 1 Soldering bath temperature: 260C max., time: 10 seconds max., number of times: 1, pre-heating temperature: 120C max. (package surface temperature) Pin temperature: 300C max., time: 3 seconds max. (per side)
Symbol for Recommended Condition
IR30-00-1
VPS
VP15-00-1
Wave Soldering
WS60-00-1
Pin Partial Heating
--
Caution: Do not use two or more soldering methods in combination (except the pin partial heating method).
Notice A model that can be soldered under the more stringent conditions (infrared reflow peak temperature: 235C, number of times: 2, and an extended number of days) is also available. For details, consult NEC.
57
PD75312(A), 75316(A)
APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS
Product Item ROM Configuration ROM (bits) 000H-FFFH 4096 x 8
PD75304(A) PD75306(A) PD75308(A) PD75312(A) PD75316(A)
Mask ROM
PD75P308
PD75P316
PD75P316A
EPROM/One-time PROM*1
0000H-177FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 0000H-1F7FH 0000H-3F7FH 0000H-3F7FH 6016 x 8 8064 x 8 12160 x 8 16256 x 8 8064 x 8 16256 x 8 16256 x 8 512 x 4 (bank 0, 1 : 256 x 4) *2
RAM (bits) 3-byte Branch Instruction Others Program Counter Mask Option 12 bits 13 bits
Instruction Set
None
Provided
Commonly provided 14 bits 13 bits 14 bits Not offered
* Pull-up resistor for Ports 4, 5 * Dividing resistor for LCD driving supply voltage
VPP, PROM Programming Pin Connections Directly Driving LED Operating Supply Voltage Range Electrical Characteristics Absolute Maximum Ratings DC Characteristics Quality Grade
None
Offered
Not offered
Offered
2.7 to 6.0 V
5 V 5%
5 V 5%
2.7 to 6.0 V
Differ in high-level output current and low-level output current
Differ in low-level output voltage
Special * 80-pin plastic QFP (14 x 20 mm) * 80-pin
Standard * 80-pin * 80-pin
Package
plastic QFP (14 x 20 mm) * 80-pin ceramic LCC w/ window
plastic QFP (14 x 20 mm)
plastic QFP (14 x 20 mm) * 80-pin ceramic LCC w/ window
*1: For the PD75P316, only the one-time PROM is provided. 2: 1024 x 4 (Banks 0, 1, 2, 3, 15 : 256 x 4)
58 4
PD75312(A), 75316(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using 5
PD75312(A) and 75316(A):
Hardware IE-75000-R *1 IE-75001-R IE-75000-R-EM *2 EP-75308GF-R EV-9200G-80 PG-1500 PA-75P308GF Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler In-circuit emulator for 75X series Emulation board for IE-75000-R and IE-75001-R Emulation prove for PD75312GF(A) and 75316GF(A), provided with 80-pin conversion socket EV-9200G-80. PROM programmer PROM programmer adapter solely used for PD75P316GF and 75P316AGF. It is connected to PG-1500. Host machine PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3 ) IBM PC/AT TM (PC DOSTM Ver.3.1)
*1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
59
PD75312(A), 75316(A)
APPENDIX C. RELATED DOCUMENTS
60
PD75312(A), 75316(A)
GENERAL NOTES ON CMOS DEVICES
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to VDD or GND through a resistor. Refer to "Processing of Unused Pins" in the documents of each devices.
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application.
61
PD75312(A), 75316(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation.
62

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